Network for obtaining a threshold function utilizing majority gates in an array



Dec. 22, 1964 R O, W|NDER 3,162,774

NETWORK FOR OBTAINING A THRESHOLDFUNCTION UTILLZINGTv MAJORITY GATES IN AN ARRAY 5 auf 0F .9 FUA/c'r/@A/ INVENTOR 00m/r Armi/vir DSG-2251964 v R'. o. WINDER 3,162,774

NETWORK FOR OBTAINING A THRESHOLD FUNCTIONSUTILIZING MAJORITY GATES IN AN ARRAY l F'iledlOct. 4,- 1961 5 Sheets-Sheet 2 INVENTOR.

Dec. 22, 1964 R o Wl R 3,162,774

NDE NETWORK FOR OBTAINING A THRESHOLD FUNCTION UTILIZING MAJORITY GATES IN AN ARRAY Filed Oct. 4. 1961 5 Sheets-Sheet 3 Alim/atx www (EA/ZES durar X, a 'lm/r f 1/ ,vim/MK aar/0r ("/m/p 6475) INVENTOR. iaf d PWA/pff BY Dec. 22, 1964 NETWORK FOR OBTAI Filed 00T.. 4, 1961 R. O. NING A THRESHOLD FUNCTION UTILIZING MAJORITY GATES IN AN ARRAY WINDER 5 Sheets-Sheet 4 INVENTOR. /afr 0, l/l//A/ofA2 Dec. 22, 1964 R. o. WINDER 3,162,774

NETWORK FoR OBTAINING A THRNsRoLD FUNCTION UTILIZING MAJORITY GATES 1N AN ARRAY 5 Sheets-Sheet 5 Filed Oct. 4, 1961 INPI/T3 Alsof@ 4/7 J#A3111 i/s United tates jPatent 'nfrce 3,162,774 Patented Dec. 22, i964 NETWRKFGR BTAELUNG A THRESHGLD FUNCTEN UfiLi/ZNG MAl'ORiTY GATES EN AN ARF-AY Robert 0. Winder, Trenton, NJ., assigner to Radio Corporation of America, a corporation of Belawarc Filed @sin 4,19%, Ser. No. 142,873 6 Claims. (Cl. SWL-88.5)

The present invention relates to networks of logic elements for performing threshold functions. While not restricted thereto, these networks are especially useful in data processing systems such as digital computers.

Logic elements employing threshold gates are in common use in the design of digital computers. For example, and and or gates are threshold gates. lThreshold gates are easy to design and may be implemented in many ways-provided the number of inputs to the gates are relatively low, In the case of a ve input gate, for example, there is a difference of 20% between the closest of two different input conditions. Circuits may be designed to within this tolerance at the present state of the art. However, where the number of inputs are large, there is no practical way, at present, to overcome the limits irnposed by engineering tolerances. For example, the design of a 100 input gate, a gate in which there is a difference of only 1% between the closest of two different input `conditions, at present, has no practical solution.

The tolerance conditions above place a severe restriction on the logical designer. computer or switching network in terms of gates which have a limited number of inputs even though gates or networks with larger numbers of inputs, if available, might provide a much better system.

The object of the present invention is to provide net-v works which can realize any arbitrary threshold function.

The elementary building blocks of the present invention are majority gates. A majority gate is defined as one which produces an output which is equal to the majority of its inputs. The principles of the invention are applicable to the use of three input, five input, seven input or higher number input gates. The gates are arranged in a regular network in a Way vdiscussed in greater detail below and the network can realize any desired threshold function. The fact that the networks are regular is an important advantage as it permits the network easily to be manufactured as, for example, in batchprocesses.

The invention is described in greater detail below and is illustrated in the following drawings of which:

FIG. 1 is a diagram of a majority gate and the Boolean equation for the gate;

FIG, 2 is a drawing which is useful in explaining the operation of the invention;

lFIG. 3 is a schematic drawing of a network which realizes a out of 9 threshold function;

FIG. 4 is a generalized schematic drawing of a network employing three input majority gates which realize a t out of n logic function;

FIG. 5 is a schematic drawing of a network which realizes a 7 out of 9 threshold function;

FIG. 6 is a schematic drawing of realizes a 3 out of 9 threshold function;

FIG. 7 is a schematic drawing -of realizes a 2 out of 1l threshold function;

FIG. 8 is a schematic drawing of a network which realizes an 1l out of l1 threshold function;

FIG. 9 is a schematic drawing of a network employing five input majority gates which realize a 5 out of 9 threshold function; and

FIG. 10 is a table to help explain the operation of the network of FIG. 3.

a network which a network which He is forced to design a -the gures is a majority gate.

The definitions and general discussion vwhich follows are helpful in understanding the figures above.

An elementary building block employed throughout This gate is well-known and may be implemented with diodes, transistors, magnetic devices, cryoelectric circuits, or in other ways. A lmajority gate has an odd number of inputs. It produces an output which is equal to the value of the majority kof the inputs. The Boolean equation for majority `gate having inputs AyB and C and an output D is given in FIG. 1.

As implied above, a majority gate receives signals indicative of binary bits and produces an output signal indicative of a binary bit. When an input or output sig- Vnal is at one level, it represents the binary bit one and when it is at another level, it represents'the binary bit zero To simplify the discussion, rather than speaking of electrical signals lapplied to gate elements in a network, it is sometimes stated hereafter that a one or a zeroisy applied to the gate or network.

The networks ofthe present invention realize threshold functions. A typical threshold function may be4 a t out of n function. n represents the total number of arguments or inputs. t is a number not larger than ,n and represents the least number of arguments which must have the value l to produce a result of 1. In terms of a physical circuit, n represents the number of inputs indicative of binary digits applied to the circuit; z is the smallest number of inputs representing the binary bit onelrequired to produce an output indicative of a one A t out of n threshold function is sometimes written t/n in the discussion which follows.

`Throughout the figures capital letters are used to represent signals indicative of binary bits. Forexample, X2 may represent the binary bit one or the binary bit zero.

For the sake of drawing simplicity, the invention is illustrated in most of the drawings in terms of networks in which n, the number of inputs, is 11 or less. vHowever, it should be appreciated'that n can be any arbitrarily large number such as or much more than 100 and it is intended that the simplified drawings not be con- Strued as limiting the invention to networks in which n Vis a relatively small number.

The networks of the present invention are made up of elements (gates) arranged in rows and diagonals as i1- lustrated schematically in FIG. 2. There are n rows` of elements and t diagonals shown and each diagonal, ex-

cept 4the first, 4has (n-'t-j-l) elements. lThese elements are represented as circles in FIG. 2.

The first element in each diagonal is the one in the 'jth row in which j=z`. j is a parameter which represents one of 4the n rows and, in the example shown, can have any l"value from 1 to n. z' is a'parameter which represents one of the diagonals and, in the example shown, can have a value from l to it. As an example of this nomenclature, the second element on the second diagonal is in row 3. This element lies at the intersection =2,` j=3 and is sometimes referred to as gate 2/3.

The last element on each diagonal, in the example shown, is located in the row in which j=rL-t-|-. For' example, Vthe last element in the third daigonal lies in row 6.

XI-Xg. The inputs Xi and X2 are applied to the ,elements in the second row. The inputs X3 are applied to the elements in the third row. The inputs X., are applied to al1 elements in theV fourth row. The inputs X5 are applied to all elements in the fth row and` so on. In the eneral case of networks employing three-input majority gates, it maybe stated that the gates in the jth row receive as one input the jth one of the n input signals.

A gate such as the one legended 3/5 receives `as Aa second input the output of a gate in the preceding row and same diagonal (the gate legended 3/4), and as a third input, the output of a gate in the preceding row andthe preceding diagonal (gate 2/4). In the general case of networks employing three-input majority gates,

from the gate at the intersection of the i diagonal and the,

j-1 row and also a signal from the gate at the intersection of the-l diagonal and the j-1 row.

The limiting case of the rule expressed immediately above is the one in which the gates lie at i=j (gates 2/2, 3/3, 4/4 and 5/5) and the gates on diagonal =1 (gates 1/2,.1/3, 1/4 and 1/5). For the case in whichj=z',-a signal indicative of the binary bit zero is applied to the 1'/ j gate rather than a signalfrom a gate at the z' diagonal and the j-l row.. For example, in the case of the 3/3 gate, there is no gate on the third diagonal and second row. Accordingly, the binary bit zero is applied to the 3/3 gate instead. In the case in which i: 1, a signal indicative of the binary bit` .one rather ythan a signal in the z'-1 diagonal is applied to the /]l gate. For example, in the case of the gate 1/4 whichappears on ,the first diagonal, there isno diagonal to the left of the first diagonal and accordingly, there is no gate in row 3 to the left of the 1/3 gate. Accordingly, a 1 is applied to the 1/4 gate rather than a signal `from the non-existent /3 gate. Y

In the network of FIG. 3, the gate at the apex of the network may be omitted or may be present. If the gate were present, it would receive as its three inputs 1, X1 and 0. Accordingly, the output of this gate wouid equal the value of X1. Since the output and input of this gate would be equal, this gate may be omitted and X1, instead,

applied directly to the gates in the second row as is shown in FIG. 3.

The legends applied to each gate refer to the functionv they perform individually with respect to the input variables. For example, the gate legended 1/2 produces a 1 output when either one or both of the .two preceding variables which affect thegate have the value 1. In

` Boolean terms, the equation for this gate is X 1-l-X 2. The Lgate legended 2/2 producesa 1 output only when two of Coincidentally, as pointed out above, the legend applied to each gate refers to the diagonal and row in which each gate is located. For example, the 1/2 gate is located on `the first diagonaly and second row. The 4/6 gate is located on the fourth diagonal andv sixth row.

It can be proved mathematically that the network vof FIG. 3 realizes the 5 out of 9 function. However, the operation of the network may perhaps more clearly be understood by giving specific examples. This is done in the table of FIG. 10.` Three random samples of values for the input variables have been chosen for illustration.

In` the first case, ve of the nine variables are y1 and remaining four are 0.` The network output is shown to be 1. In the second case, six of the input variables are 1 and the remaining three are 0 and again the network output is shown to be l. In the last case, three of the ceives Xt as its input.

variables are 1 and the remaining six are O and the network output is shown to be O.

A drawing of a three input majority gate logic network for realizing any threshold function (t out of n) is shown in FIG. 4. As in the network of FIG. 3, the majority l of the array is in row n-'t}1 and it receives the input variable X(n t+1). The output of the network is taken from the element in the last row of the array. This output is t out of n. The total number of gates in the network is (nr+1)t-l.

FIG. 5 shows a network designed in accordance with the teachings of FIG. 4 which realizes a 7 out of 9 threshold function. This network employs three input major.- ity gates. The yoperation'of this networkcan easily be deduced from they previous discussion of FIG. 3 andit can also be proved mathematically.

FIG. 6 shows a network designed according to the teachings of the invention which realizes a 3 out of 9 function. Three input majority gates are employed.

FIGS. 7 andS have been included to show the generality of the present invention. The network of FIG. 7 which employs three input majority gates realizes a 2 out of 11 threshold function; the network of FIG. 8 which also employs three input majority gates, realizes an 1l out.

of 11 network. The network of FIG. 11 is, of course, an and gate. The limiting case in the other direction, namely .1 out of` 10 is, of course, an or gate and is easily Irealizable according to the teachings of FIG. 4.

All of the networks discussed so far realize odd threshold functions. can realize even threshold functions as well. follows from the general drawing of FIG. 4.

It is possible to use practical gates having greater than three inputs in the networks of the invention. An important advantage of networks employing gates having more than three inputs is thatfthe total number of gates in the network can be reduced. The way lin which such net* works may bel designed is discussedrnore fully below in connection with FIG. 9.

In general, to make a network in which majority gates having lgreater than three inputs Iare employed, the follow ing procedure is followed. Lety m equal the number of The design inputs to each gate. As already discussed, Afor a majorityl gate as dened here, m is an odd number. Next, the network for realizing the desired threshold function is` drawn employing the. three input gates .already discussed. For example, vif. it is desired to realize a 5 outof 9 threshold function, the network of FIG. 3 is drawn. Solve-the equation In the illustrative case of 111:5, k=2. A check is then placed next to the bottom row of the network (the ninth row in the case of FIG. 3), and then working upwards every kth rowfthereafter is checked. 111:5, every other row is checked. If m=7, every third row ischecked and so on. Next, all of the gates in each unchecked row are deleted. The new inputs to any gate are:

(1) The X input signal which previously venteredthe gate.

(2,) The X input signal which previously entered the gate in the preceding rows which have been deleted.

(3) The outputs of the gatesof the new row (now immediately above) which in the old network intluenced this gate.

The element in the left corner The invention is, however, general and If, for example, i

(4) If a gate is too near the upper right or the upper left (or both) edges of the network, there will not be a sutlcient number of appropriate gates in the row-precedingit to provide m inputs to thatgate. In this case, a zero is supplied for each input called for from a nonexistent gate to the right of the network, -a one is supplied for each'input called for-from a non-existent gate to the left of thel network; inv they case in which the gate is equidistant from the upper right and ileft edges, equal numbers ofvonesan'd zeros are applied so that the ones Vand zeros offseteach other.

A network. designed in accordance with the procedure above is illustrated in FIG. 9. This ligure shows a network employing lve input majority gates which realize a out of 9 function. ComparingFIG 9 withFIG. 3, it may be seen that the eighth, sixth, fourth, and second row ofthe network of FIG. 3 have been deleted. An element such as 32 (diagonal 3, row 2) which corresponds to element 3/ 3 of FIG. 3 receives as inputs X3, X2, X1, 0 and 0. X3 and 0 were inputs it previously received. X2 is the input which was Aformerly' applied to the 2/2 gate in the preceding row. X1 is an input which intluenced the output offormer gate v2/2 and the output gate of 2/2 inuenced the gate 3/3. Accordingly, the input X1 indirectly in'uenced the output of the 3/3 gate. For this reason X1 mustbe applied to gate BE-Qthe-gate corresponding to the 3/3 gate. Since gate 32 is at the upper right edge of the network, there isno fifth input available from a gate which is above and to the right of gate`32.

There is, therefore, `substituted for this missing input the input zero since the missing gate is to the right of the network.

Gate 22 in FIG. 9 corresponds to the .2l/3 gate of FIG. 3. Gate 22 receives as inputs X1, X2 and X3. Again X3 was received formerly by the 2/3 gate. X2 was applied formerly to the gates in the row which is'now deleted, that is, the second row. X1 formerly influenced the 2/3 gate. As gate 2.2 is a tive input gate, two more inputs must be supplied. Since this gate is equally distant from 'the upper right and left edges,the binary bits one and zero are applied to gate 22.

To further illustrate the invention, gate 44 may be chosen. Gate 44 corresponds to the 4/7 gate of FG. 3. Gate 44 receives as inputs X7 and X5. X7 was formerly applied to the i/ 7 gate; X6 is the input which was formerly applied to the sixth row (now deleted). The remaining three inputs to gate 44 come -from gates VKf2.3, k33 and 43. The outputs of the corresponding gates of FIG. 3, namely 2/5, 3/5 and 4/5 indirectly iniluenced the 4/7 gate in FIG. 3 corresponding to gate 44. Accordingly, the loutputs of gates 23, 33 and 43 must be-,ap'plied to gate 44.

It can be shown mathematically that the output of the network of FIG. 9 realizes a 5 out of 9 function. Note that there are substantially fewer gates in the network of FIG. 9 vthan the one of FIG. 3. There are 12v gates in the network of FIG. r9, 24 gates in the network of FIG. 3.

'perfectly general and are applicable to the design of any network employing majority gates regardless of the number of inputs to the gates. The `symbols employed are:

n=total number of inputs (arguments).

t=no more than n and is the number of inputs which must be 1 to produce a l output from the network.

m=the number of inputs to each majority gate in the network.

elle] FIG. 9.

5 where implies that if the term is not an integer, q is equal to the next lower integer. j=the row in which argate is located. i :the diagonal in which a gate is' located.

For a particular gate z'j l (l) The range inthe'values of'j which are possible:

max [d,e] means select the one of d and e which has the greater value, and

min [che] means selectthe one of d and e which has the smaller value (3) For j=l,`the vinputs to gate i, 1 are:

(a) The signals X1, X2 "Xpfqk, wherethef-total number of signals is (l1-qlc) (b) (k--l-l) constant l signals, and

(4) For j l, the inputs to gate z',]' are:

(a) The k signals (where k refers to the totalnumber ofsignals) (5) In the case in `which the values of and j are such that the gates which satisfy theA expressions in 4b above do not exist (because the -value is out of range):

(a) Whenever the zvalue is less than l (out of range to the left) supply instead a constant 1 signal;

'( b) Whenever the z'value is greater than the j value (out of range to the right) supply instead a constant 0 signal.

(6) lIn any case when the X input to a gateis equal toits X outputfthatvgate may be omitted, and said X input supplied instead to the gates to which the output or" the omitted gate would have been applied.

The desired output t/n is taken from the gate at f=f. f=,q+1

VThe rules above can be proved mathematically; however, the mathematics is somewhat involved and need not be Adiscussed here. Instead, it is shown below how therules apply to a specictgate in one of the networks which is illustrated, namely*` gate 4t3 in the-network of (The rules apply, ofcourse, to .alll gates in all networks shown.) Applying the rules above yto this gate:

Put into words, the values l through 5 are possible for j. This checks.

Put into words, there are fivev possible diagonals (i) namely l-5, on which agate'in the third row (j=3) may lie. This checks.

(3) For j=1, the total number of input signals is nqk=l. This checks.

(a) These signals are 7 X1 Xn qk (b) (lc-i+1) constant 1 signals =(2\-1|-,1)=2 constant 1 signals (Note that when j=l, z`=1) l (c) [(q-{-1)k-n+i] constant 0 signals :2 constant 0 signals summarizing, the gate in row 1 has as inputs: 0,(),l,1,X1. Since the two kzeros oiset the two ones, the output f this gate isX1 and this is equal to the input signal X1 to the gate. Accordingly, the gate in row 1 may be omitted (see 6 above). This checks with FIG. 9 in which the gate in row 1 is omitted.

(4) for j 1 (in this case j=3) the inputs are:

(a) The k (in this case 2) signals This checks with FIG. 9.

(b) The outputs from :the k+1 (in this case 3) gates Therefore, substitute 0 yfor this input to gate 43,l as required by b above, since j z'. This also checks with FIG. 9 because gate 43 in FIG. 9 receives as inputs they outputs of gates 22 and 32, and 0.

The `various networks illustrated and discussed above.

realize t out ofn threshold functions. The networks are ,shown as having only one output, located at one corner of the network.r It should be appreciated that many more than one output may be taken from the network, if desired, and that such multiple output networks are useful as logic circuits.y Further, in some practical applications,-it may betcheaper to mass produce one particular network suchas the one of FIG. 3, for example, to obtain any one or more of logic functions such as 3/7, 4/7, 5/7, 5/8 and so on, than to specically design a diterent optimum circuit for eachdifferent threshold function. These different functions are available from the circuit of FIG. 3 at the outputs of the gates legended 3/7, 4/7 and so on.

Inthe case in which m, the number of inputs to a gate,

is 3, it is possible slightly to simplifyy the bottom halfy of the network (the rows below the (rt-t+1) row and below the t row (see FIG. 4)). The last gate is eliminated from each alternate row beginning with theV (f1-1)' row and going up. In a row from .which a gate has been eliminated, the remaining gate or gates each receive asV one input the signal XJ, Ywhere j is the row from which a gate has been eliminated, as another input thel output of the gate Vin the preceding row and inthe diagonal +1, where i is the diagonal on which a gate in question is located, and one output from the gate in the preceding row and in the diagonal -z'-1. The gate or gates in the rows j+1 below the rows from which a gate has been eliminated receive as inputs: the signal Xj+1 the outputV of the gate in the preceding diagonal -l and row j-1, and the output of the gate in the preceding diagonal i-l and row j.

Following the procedure above, the network of FIG. 3, for example, is reduced by two gates. One is eliminated from row 8 and one is eliminated from row 6.' The 2/6 gate receives inputs X6, youtput of 1/5, and output ofv 3/5; the 4/6 gate receives as Iinputs X5, Voutput of 3/5, output of 5/5; the 5/6 gate is deleted.v The 3/7 gate receives as inputs X7, output of 2/ 6, output of 2/5, and sof n La on. A disadvantage of optimizing the number of gates in `this way is that the network is no longer symmetrical.

What is claimed is: 1. A network for performing a t out of n threshold function comprising a plurality of interconnected m input majority gates, means for applying input signals in'-V dicative of input variables to saidgates; means for applyingY fixed inputs indicative of the binary bit one to some of said gates; means for applying iixed inputs indicative of the binary bit zero to some of said gates; and means for deriving an output from one of said gates indicative of the presence of t out of n inputsto said network, where t and n are, integers, and m is anodd integer.

2. An array of m input'majority gates forperforrn.- ing a t out of n logic function, said gates being arranged in diagonals and j rows where:

. (l) the range in values of j which are possible is:

(3) for j: 1, the inputs to gate i, 1 are:

(a) the signals X1, X2 Xn qk, where the total number of signals is n-qk, (b) (Ic-i+1) constant 1 signals, and (c) [(q-{1)'k*nli]rconstant 0 signals: (4) for j 1, the inputs to gate j are:

(a) the k signals X (q j+2)k+1,

(5) in the-case in which the values of i and j are such that gates `which satisfy the expression in 4b above do not exist (because the z'value is out of range):

(tz) whenever the z'value is less than 1, supply instead a constant 1 signal, and

(b) whenever the i-value is greater than the j value, supply instead a constant t) signal (6) in any case where the X input to a gate is the X ouput, that gate may bey omitted and said X supplied instead to the gates to which the youtput of the omitted gate would have been applied: where: n=total number of inputs to the array t=not more than n m=an odd integer :[nl] q "'-k where implies that if the term is some, integer plus a fraction, the fraction is dropped; and the gate at z'=t, y=q1 produces the desired `output t/n.

3. An array of three-input gates for performing; a l out of n logic function comprising, a plurality of gates arranged lin positions electrically corresponding to n rows and t diagonals, the gate at the intersection of the ith diagonal and jth row, hereafter termed the ij gate, re-,

ceiving as inputs, a signal indicative of the ith one of n input signals, a signal from the gate at the intersection of ith diagonal and the j-l row, and a signal from the gate at,the intersection of the -l diagonal and the j-l row, except that in the limiting case in which i=l, a signalindicative of the binary .bit one rathery thana signal from'a gate in the i-1 diagonal is applied to the z'j gate, in the limiting case in which j=z', a signal indicative of the binary bit zero is applied to the ij gate rather than a signal from a gate at the z diagonal and j-l row, and in the limiting case in which j== 1, the gate at this intersection may be omitted, and the rst one of the n signals applied as inputs to the gates in the second row, where j is a digit from 1 to n and z' isa digit from 1 to t.

4. An array of gates for performing a t out or" n logic function comprising, a plurality of three-input majority gates arranged in positions electrically corresponding to n rows and t diagonals, the Iirst gate on each diagonal being located in the jth row in which j=z` and the last gate on each diagonal being located in the jth row in which j=n-z+i, where j is an integer from 1 to n and z' is an integer from 1 to t and refers to one of the t diagonals, the gate at the intersection of the z'th diagonal and jth row, hereafter termed the ij gate, receiving as inputs, a signal indicative of the jth one of n input signals, a signal from the gate at the intersection of ith diagonal and the j-l row, and a signal from the gate at the intersec- 15 tion of the z`l diagonal and the j-l row, except that in the limiting case in which z`=1, a signal indicative of the binary bit one rather than a signal from a gate in the i -1 diagonal is applied to the ij gate, in the limiting case in which j=z', Ia signal indicative of the binary bit zero is applied to the ij gate rather than a signal from a gate at the i diagonal and ]`-1 row, and in the limiting case in which j=i= l, the gate at this intersection may be omitted, land the irst one of the n signals applied as inputs to the gates in the second row.

5. An array of m input majority gates which is capable of performing t out of n and other threshold logic functions, said gates being arranged in positions electrically corresponding to z' diagonals and j rows where:

(l) the range in values of j which are possible is:

(2) the range in values of z' which are possible is:

maX[1, t-(q-H-1)k]imin[n-(q-jl1)k, t]

(3) for j=1, the inputs to gate z', 1 are:

(a) the signals X1, X2 Xn qk, where the total number of signals is n-qk,

(b) (Ic-i+1) constant 1 signals, and

(c) [(q-i-Ulc-n-l-i] constant 0 signals: (4) for j 1, the inputs to gate i, j are:

(a) the k signals X (q j+2)k+1,

it@ (b) the outputs from the k+1 gates: F1), (1k+1,J'-1) (iii-1) (5) in the case in which the values of z' and j are such that gates which satisfy the expression in 4b above do not exist (because the z'value is out of range):

(a) whenever the -value is less than 1, supply instead a constant 1 signal, and

(b) whenever the z' Value 4is greater than the j value, supply instead a constant O signal.

(6) in any case where the X input to a gate is the X output, that gate may be omitted and said X supplied instead to the gates to which the output of the omitted gate would have been applied:

where:

(ll-k) n=tota1 number of inputs to the array t=not more than n m=an odd integer n l efekwhere implies that if the term is some integer plus a fraction, the fraction is dropped.

6. A network for performing threshold functions comprising a plurality of interconnected m input majority gates; means for applying input signals indicative of input variables to said gates; means for applying fixed inputs indicative of the binary bit 1 to some of said gates; means for applying fixed inputs indicative of the binary bit O to some of said gates; and means for deriving a plurality of concurrent outputs from said network indicative of threshold functions of said input signals in the range one out of two to t out of n, where n is an i11- teger which is equal to the number of input variables, t is Ian integer which is not greater than n, and m is an odd integer.

References Cited in the le of this patent UNITED STATES PATENTS 

1. A NETWORK FOR PERFORMING A T OUT OF N THRESHOLD FUNCTION COMPRISING A PLURALITY OF INTERCONNECTED M INPUT MAJORITY GATES, MEANS FOR APPLYING INPUT SIGNALS INDICATIVE OF INPUT VARIABLES TO SAID GATES; MEANS FOR APPLYING FIXED INPUTS INDICATIVE OF THE BINARY BIT "ONE" TO SOME OF SAID GATES; MEANS FOR APPLYING FIXED INPUTS INDICATIVE OF THE BINARY BIT "ZERO" TO SOME OF SAID GATES; AND MEANS FOR DERIVING AN OUTPUT FROM ONE OF SAID GATES INDICATIVE OF THE PRESENCE OF T OUT OF N INPUTS TO SAID NETWORK, WHERE T AND N ARE INTEGERS, AND M IS AN ODD INTEGER. 